A 0 . 8 m CMOS Delayed Locked Loop for Sub - 500 ps Clock
نویسندگان
چکیده
Yong-Bin Kim* Tom Chen** *Microelectronics Division Samsung Electronics Co. San Jose, CA, USA **Department of Electrical Engineering Colorado State Univ. Fort Collins, CO 80523, USA Abstract This paper describes a CMOS variable delay line Delay Locked Loop(DLL) circuit speci cally designed for reducing clock skew on DRAM/Logic merged integrated circuit using 0.6 m CMOS process. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line of the programmable DLL is between six and eighteen stages depending on the program mode, which reduces 1ns to 3ns clock skew to below 400ps for clock frequencies from 50MHz to 150MHz. The chip size is 0.55 X 0.65 mm2 including bonding pads.
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